A nonvolatile memory retains stored data without deleting the stored data even when power supply is interrupted. A flash memory, which is a typical nonvolatile memory, includes two gate layers stacked in a single cell transistor. The gate layers are called a floating gate and a control gate.
Typical operations of a flash memory may be divided into a program operation, an erase operation, and a read operation.
The program operation includes trapping electrons in a floating gate, thus resulting in an increase in threshold voltage of a cell transistor. Also, the erase operation includes transporting charges trapped in the floating gate to a channel region or source and drain regions. The erase operation may result in a decrease in threshold voltage of the cell transistor.
That is, a data storage type of a flash memory may be embodied by variations in threshold voltage. Also, in order to enable a program or erase operation, charges should pass through a tunneling oxide layer disposed between a channel region and a floating gate. This may be accomplished by Fowler-Nordheim (F-N) tunneling or hot carrier injection.
F-N tunneling refers to transportation of charges due to a difference between a voltage of a bulk region disposed under a channel and a voltage of a floating gate. Also, hot carrier injection refers to a phenomenon in which charges accelerated due to a voltage difference in a source or drain region pass through a tunneling oxide layer due to a voltage applied to a control gate.
An F-N tunneling operation may be disadvantageous in terms of an operating time. In particular, since a NAND flash memory performs program and erase operations through F-N tunneling, the NAND flash memory operates at a lower speed than a NOR memory. However, despite the low operating speed, the NAND flash memory is appropriate for storage of voice or image data because the NAND flash memory is capable of reading data in page units.
In recent years, techniques on flash memory devices in which cells are disposed as NAND types and perform NOR-type operations have been proposed as exemplarily disclosed in U.S. Patent Publication No. 2007-236994. Hereinafter, the technique disclosed in U.S. Patent Publication No. 2007-236994 will be referred to as a conventional art.
FIG. 1 is a cross-sectional view illustrating program and erase operations of a conventional memory cell.
Referring to FIG. 1, the memory cell includes a source region 100 and a drain region 110 formed on both sides of a channel region and a gate structure 130 formed on the channel region.
The gate structure 130 includes a tunneling oxide layer 131, a charge trap layer 133, a blocking insulating layer 135, and a gate electrode 137. Also, the source and drain regions 100 and 110 are heavily doped with n+impurity ions, and a p-well 120 is formed outside the source and drain regions 100 and 110. Thus, a p-n junction is formed between the p-well 120 and the source and drain regions 100 and 110, and a depletion region is formed at an interface of the p-n junction. Also, when an additional bias voltage is not applied to the source region 100 or the drain region 110, a built-in voltage Vbi is generated across the depletion region.
The program operation of the memory cell having the above-described structure will now be described. To begin with, a voltage Vg of 0 V is applied to the gate electrode 137, and a voltage of 9 V is applied to the p-well 120. A voltage of 9-Vbi is applied to a portion of the source or drain region 100 or 110 adjacent to the depletion region due to the voltage of 9 V applied to the p-well 120.
Thereafter, a voltage of 0 V is applied to the p-well 120, and a voltage Vg of 9 V is applied to the gate electrode 137. Since the voltage of 9-Vbi was applied to the source or drain region 100 or 110 and the voltage of 0 V was applied to the p-well 120 under previous bias conditions, a reverse bias voltage is applied to the p-n junction between the p-well 120 and the source and drain regions 100 and 110. Thus, due to the reverse bias voltage, electrons of the source or drain region 100 or 110 may overcome a potential bather between the source or drain region 100 or 100 and the depletion region and move to the channel region.
Also, the electrons in the channel region may pass through the tunneling oxide layer 131 due to the voltage Vg of 9 V applied to the gate electrode 137 and may be trapped in the charge trap layer 133.
During the erase operation, the memory cell performs a complementary operation to the program operation. To begin with, a voltage Vg of 0 V is applied to the control gate 137, and a voltage of 9 V is applied to the p-well 120. Thus, a voltage of 9V-Vbi is applied to the portion of the source or drain region 100 or 110 adjacent to the depletion region.
Subsequently, a voltage of 0 V is applied to the p-well 120, and a voltage Vg of −9 V is applied to the gate electrode 137. Due to the bias voltage of 0 V applied to the p-well 120, a reverse bias voltage is applied between the source and drain regions 100 and 110 and the p-well 120. Also, due to the voltage Vg of −9 V applied to the control gate 137, holes are trapped in the charge trap layer 133 across the channel region, thereby enabling the erase operation.
FIG. 2 is a circuit diagram of a conventional flash memory performing program and erase operations.
Referring to FIG. 2, a bias voltage is applied to a p-well of a memory cell during a program operation in response to string selection transistors SST0, SST1, and SST2 being turned on.
For example, a voltage of 9 V is applied to bit lines BL1 and BL2 of the string selection transistors SST1 and SST2 included in a selected string, while a voltage of 0 V is applied to a bit line BL0 of an unselected string. Also, a voltage of 11 V is applied to a string selection line SSL.
Accordingly, the string selection transistors SST0, SST1, and SST2 are turned on, a voltage of 9 V is transmitted to first terminals of memory cells M10 and M20 of the selected strings, and a voltage of 0 V is transmitted to a first terminal of a memory cell M00 of the unselected string. In addition, the voltages transmitted to the bit lines BL0, BL1, and BL2 through the string selection transistors SST0, SST1, and SST2 are electrically transmitted to p-wells of memory cells.
Furthermore, a voltage of 9 V is applied to a word line WL1 of memory cells M11 and M21, which are programmed in the selected string. That is, the voltage of 9 V is transmitted through the word line WL1. Conversely, a voltage of 0 V is applied to word lines WL0 and WL2 of the remaining memory cells, which are not programmed.
When selected memory cells are erased, a voltage of −9 V is transmitted through the word line WL1 so that an erase operation may be performed as shown in FIG. 2. Thus, the selected memory cells M11 and M21 may be discretely erased.
In other words, the flash memory of FIG. 2 may discretely select and program a memory cell and discretely select and erase a memory cell. That is, the flash memory of FIG. 2 may perform a NOR-type operation during program and erase operations.
It can be seen that although the circuit of FIG. 2 is configured to be a NAND type, the circuit of FIG. 2 may substantially perform a NOR-type operation during program and erase operations.
FIG. 3 shows cross-sectional views of a string structure of the circuit of FIG. 2.
Referring to FIG. 3, a butting contact 140 should be included to enable the operations of FIG. 2.
Specifically, in order to supply a bias voltage from a bit line BL through a string selection transistor SST to a p-well 120, the flash memory should include the butting contact 140 formed of a conductive metal on the surface of a substrate. This is because, since the string selection transistor SST is an n type and memory cells are n-types, the bias voltage cannot be directly transmitted to the p-well 120. That is, an ohmic contact is required to transmit the bias voltage to the p-well 120, and the bias voltage should be transmitted through an additional p-type doped region to be in ohmic contact with the p-well 120.
Thus, the conductive butting contact 140 is disposed on an n+doped region 141, which is an output terminal of the string selection transistor SST, and a p+ doped region 143 is disposed under one terminal of the butting contact 140.
The above description should be applied likewise to an erase operation.
FIG. 4 illustrates the layout of the circuit of FIG. 2, which is formed on a semi-conductor substrate.
Referring to FIG. 4, each of strings 150 defines an active region and includes a p-well 120 surrounding the active region. Also, a p+ doped region 143 is disposed on one side of a string selection line SSL, and a butting contact 140 is disposed on the p+ doped region 143. Respective memory cells are defined by word lines WL0, . . . , and WL7, which are disposed across the active region, and n+doped regions disposed on both sides of the word lines WL0, . . . , and WL7. It may be understood that the word lines WL0, . . . , and WL7 are equivalent to the gate electrode of FIG. 1.
The above-described structure may embody NOR-type operations without using F-N tunneling. However, the above-described structure should include the butting-contact 140 to apply a bias voltage to the p-well 120. Also, each of the strings 150 should include an additional p-well 120.
Due to the butting contact 140 included in each of the strings 150, the memory area of each page should be increased, and an additional fabrication process should be performed. That is, the burden of an additional process of forming the butting contact 140 is increased. Also, since the additional p-well 120 should be formed in each of the strings 150, there is a deviation in dopant concentration of the p-well 120 in the strings 150.
When the deviation in dopant concentration of the p-wells 120 occurs, even if a program voltage is applied to a single word line, there may be a deviation between program and erase intensities of a memory cell connected to the word line. In other words, even if a voltage is applied to the same word line, the deviation in dopant concentration of the p-wells 120 may lead to a deviation in threshold voltage of the memory cell.